Optimising the compiler for a particular hardware architecture basically means the process of tuning the output of a compiler to maximise the efficiency of an executable program. The concept of a reconfigurable computing has been around since the 1960s consisting of a standard processor and an array of "reconfigurable" hardware. In the last decade there has been a recent renaissance in this area of research with many proposed reconfigurable architectures developed both in industry and academia. Nevertheless, the development of reconfigurable hardware architecture is only one side of the problem, often overlooked is the importance of appropriate software tools that are essential for the programmability of the system and gaining the maximum performance. These existing compilation techniques for traditional architectures need to be adjusted to reconfigurable architectures. This creates a whole new set of challenges. Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. It is currently more a challenging to move to multicore for software development than it is for hardware development. Compilation techniques need to support multi-threading using higher level of abstraction (e.g. OpenMP) to simplify the expression of parallelism. The compiler efforts are focused on a profiling-driven approach that supports both loop-level and instruction-level parallelism with speculation, source-to-source code transformations, compiler-level transformations, both static and dynamic compilation techniques, and related compiler and dynamic techniques for managing scalable on-chip communication.

Current research activities

Our research interests include a wide range of code transformations and mapping techniques for programs described in high-level programming languages to reconfigurable architectures or multicore architectures. Our current concrete target is reconfigurable instruction cell array (RICA), but the compiler technologies are retargetable to similar architectures.

This research works involved:

• Porting a RICA architecture to the GCC-backend compiler and Optimizing the GCC Suite for the RICA architecture
• Investigation and Implementation of a operation chaining reconfigurable scheduling algorithm (CRS) based on the list scheduling
• Investigation and Implementation of an task mapping and scheduling algorithm targeted on the multi-core architectures