Since the appearance of the first Field Programmable Gate Array (FPGA) in 1985, the market of FPGA technology has rapidly evolved because of the high demands on such technology. This situation has encouraged manufacturers to accelerate the development pace of FPGAs. The currently available FPGAs can implement large powerful systems because of the high density of reconfigurable logic resources in a single chip. Compared to other processing platforms, FPGAs are comprehensive devices that combine flexibility and high performance in the same platform. They have a comparable flexibility to General-Purpose Processors (GPPs) because of the reconfigurability of their hardware resources. Moreover, because of the hardware parallelism and dedication, the performance is comparable to that of Application Specific Integrated Circuits (ASICs). The flexibility of modern FPGAs is further enhanced by introducing the Dynamic Partial Reconfiguration (DPR) feature, which allows for changing the functionality of part or parts of the system through the Internal Configuration Access Port (ICAP) while other parts are functioning. This feature enables the application to reuse the hardware resources by swapping different tasks in and out in a time-multiplexing manner.
Digital image processing is a field that has significant market potential. The demand for high-performance and flexible solutions for image processing makes way for FPGA to accommodate this position in the near future as the FPGA field rapidly evolves. The use of FPGAs as accelerators for image processing outperforms most of the current solutions with relatively low cost and low power consumption compared to GPPs and Graphics Processing Units (GPUs). Current FPGA solutions try to load part of the imaging application that needs high computational power on dedicated reconfigurable hardware accelerators while other parts are working on the traditional solution to increase the system performance. Moreover, the use of the DPR feature enhances the flexibility of image processing further by swapping accelerators in and out at run-time, which allows for upgrading and changing the working standards as well as achieving higher computational density compared to static implementations. In addition, the ICAP is used to port fault mitigation techniques, which enables imaging applications to work in harsh environments such space or radiation areas following the fact that FPGAs are sensitive to radiation and extreme conditions.
Our work investigates the adoption of FPGAs in the field of digital image processing to implement high-performance, low-power, flexible designs using different implementation techniques. Moreover, it investigates the advantages of using such a platform over others. It also investigates the use of the DPR feature to expand the cycle of possible imaging applications. In this context, it discusses the use of FPGAs to accelerate the Image Processing Pipeline (IPP) stages, the core part of most imaging devices. The novelty in these implementations is summarised in the following: the use of a hardware environment to increase the parallelism and achieve high flexibility, and the use of DPR to increase the performance and reduce the power consumption and area utilisation. The following are the contributions of our work: An implementation for Adams Hamilton Demosaicing algorithm for camera colour interpolation, which exploits the FPGA parallelism to outperform other equivalents, is presented. In addition, it describes an implementation for Automatic White Balance (AWB), another IPP stage, which employs the DPR feature to prove the earlier mentioned novelty aspects. Furthermore, the DPR feature is used to develop a novel flexible imaging system that requires less logic and can be implemented in small FPGAs. The system can be employed as a template for any imaging application with no limitation. Moreover, discussed in our work is a reliable version of the imaging system that adopts novel techniques including scrubbing, Built-In Self Test (BIST), and Triple Modular Redundancy (TMR) to detect and correct errors using the ICAP primitive. These techniques exploit the datapath-based nature of the implemented imaging system to improve the system's overall reliability. Our work presents a proposal for integrating the imaging system with the Robust Reliable Reconfigurable Real-Time Heterogeneous Operating System (R4THOS) to get the best out of the system. The proposal shows the suitability of the proposed DPR imaging system to be used as part of the core system of autonomous cars because of its unbounded flexibility.
Publications
An Efficient Implementation of the Adams-Hamilton’s Demosaicing Algorithm in FPGAs
Khalifat. J, Ebrahim. A, Arslan. T
In 10th International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC 2014), pp. 205-212, 2014
A Novel Dynamic Partial Recon guration Design for Automatic White Balance
Khalifat. J, Arslan. T
The NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 9-14, 2014
A dynamic partial reconfiguration design for camera systems
Khalifat. J, Ebrahim. A, Adetomi. A, Arslan. T
The NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 1-7, 2015
